The present invention relates generally to integrated circuit design. More particularly, it relates to a software method for running an analysis tool to identify design violations.
In the field of integrated circuit (IC) design and particularly very large scale integration (VLSI) design, it is desirable to test the design before implementation and to identify potential violations in the design. Before implementation on a chip, the design may be stored in a computer memory. The computer system may store information about specific signals and devices, such as transistors, that are part of the design. This information may include the connections between devices and the types of conducting segments that link devices.
Based on the connection and device information, the designer may perform tests on the design to identify potential problems. For example, one portion of the design that might be tested is the conducting material on the chip. Representations of individual metal segments may be analyzed to determine whether they meet certain specifications, such as electro-migration and self-heating specifications. Other examples of testing include electrical rules checking tests, such as tests for noise immunity and maximum driven capacitance, and power analysis tests that estimate power driven by a particular signal and identify those over a given current draw. These tests may be performed using software tools such as electronic computer-aided design (E-CAD) tools.
Existing methods apply the E-CAD test tool to each segment in the design, which can be a time-intensive process. The tool identifies violations of specifications and alerts the user of particular problems. The user then attempts to solve the problems through re-design, or may change the specifications for particular violations. For example, the E-CAD tool may perform its initial analysis assuming a worst-case scenario. In some types of analyses, the worst-case scenario may mean the maximum load on a particular segment. If the analysis is of the current through a particular segment, then the tool may assume that all connected devices are driving that segment simultaneously. In fact, this situation might be impossible if, for example, the design does not allow all of the devices to drive the segment at the same time. In this case, the designer may clear the violation by using the E-CAD tool to adjust the design specifications on a segment-by-segment basis.
Once the first analysis is completed and the designer has attempted to resolve all violations, the E-CAD tool must be run again to determine whether the adjustments resolved all violations, or whether further re-design or analysis is required. Existing methods perform subsequent analyses by re-running the tool on all signals in the entire circuit or a blocked portion thereof. As explained, this is a time-intensive process because the design may contain millions or more signals and segments to be analyzed. What is needed is a more efficient method of analyzing a design.
A method is disclosed for analyzing a VLSI circuit design stored in a computer system. Each segment of the design layout is stored in the computer memory for analysis and implementation. An electronic computer-aided design (E-CAD) program is used to analyze the design. First, the E-CAD tool is run on the entire design or on a designated part thereof. The tool compares the design to specifications and returns a list of violations on a segment basis. The tool may analyze, for example, current through each segment under worst-case scenarios to ensure that the design meets specification. The E-CAD tool identifies violations for the designer to fix through redesign or clarification of specifications. The method marks or flags signals of those segments reporting violations. After the designer has attempted to remedy the violations, the method reruns the E-CAD analysis on those signals that reported a violation during a prior run.